One type of memory includes a controller and one or more memory devices communicatively coupled to the controller. The memory devices may include volatile memory devices and/or non-volatile memory (NVM) devices. The volatile memory devices may include random access memory (RAM) devices, such as dynamic random access memory (DRAM) devices, synchronous dynamic random access memory (SDRAM) devices, double data rate synchronous dynamic random access memory (DDR-SDRAM) devices, low power SDRAM (e.g., MOBILE-RAM) devices, or other suitable memory devices. The non-volatile memory devices may include RAM devices, such as flash memory devices, resistive memory devices (e.g., phase change memory devices, magnetic memory devices), or other suitable RAM devices. The non-volatile memory devices may also include read-only memory (ROM) devices, such as programmable read-only memory (PROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, or other suitable ROM devices.
A memory including a controller and one or more memory devices may include a single data bus, which is shared between all the memory devices and coupled to the controller. The controller writes data to each of the memory devices and reads data from each of the memory devices through the shared data bus.
A typical power-up sequence for the memory proceeds as follows. First, power is applied to the controller. With power applied to the controller, the controller starts to power-up the memory devices. After a short time, the controller supply voltage, such as VDD, becomes stable. A short time after the controller supply voltage stabilizes, the controller clock becomes stable. Then, after a set time from the stabilization of the controller clock, such as 200 μs, the controller can begin accessing the memory devices. The wait time between the controller clock stabilizing and the controller beginning to access the memory devices is provided to insure that all the memory devices have completed their power-up sequences.
Typically, DRAM devices complete their power-up sequences earlier (e.g., at about 100 μs) than the controller wait time. In addition, the power-up sequences for non-volatile memory devices are typically less than for volatile memory devices (e.g., about 30 μs).
For these and other reasons, there is a need for the present invention